1. 19 Aug, 2021 1 commit
  2. 03 Aug, 2021 2 commits
  3. 21 Jul, 2021 1 commit
    • Daniel Leung's avatar
      tests: schedule_api: lengthen interval for slicing reset test · 3b369ee0
      Daniel Leung authored
      
      When calculating the expected interval for threads other than
      the first one, the test uses ms->ticks->cycles conversion to
      figure out the bound of cycles permitted. Both lower and upper
      bound conversions are using the k_*_to_*_floor32(). When
      numbers involved are not wholly divisible, decimal points are
      being truncated, resulting in incorrect intervals, and thus
      failing tests. So change the calculation to appropriate
      floor() or ceil() based on the boundary.
      Signed-off-by: default avatarDaniel Leung <daniel.leung@intel.com>
      3b369ee0
  4. 17 Jul, 2021 1 commit
  5. 29 Jun, 2021 1 commit
    • Joakim Andersson's avatar
      Bluetooth: host: Fix L2CAP sent callback on disconnected channel · 5a430eea
      Joakim Andersson authored
      
      When receiving the L2CAP sent callbacks the dynamic L2CAP channel may
      have been disconnected already. The user of the dynamic channel should
      have received the disconnected and released callbacks for this channel
      to release any resources for the data being sent, so simply ignoring
      this sent callback is enough.
      
      Fix sent callbacks by providing the CID to the callback instead of a
      pointer to potentially released memory, and lookup the CID to check that
      it is still valid.
      Signed-off-by: default avatarJoakim Andersson <joakim.andersson@nordicsemi.no>
      5a430eea
  6. 11 Jun, 2021 1 commit
  7. 14 May, 2021 1 commit
  8. 22 Apr, 2021 3 commits
  9. 13 Apr, 2021 4 commits
  10. 08 Apr, 2021 1 commit
    • Kumar Gala's avatar
      drivers: uart: uart_cmsdk_apb: fix interrupt handling · ec0aa833
      Kumar Gala authored
      
      The CMSDK uart interrupts for TX and RX can either be treated as a
      signel interrupt line or distinct interrupts for TX & RX.  In the case
      that they were distinct we didn't get the ifdef correct based on DTS.
      
      If we have 2 interrupts in DTS we assume they are for TX & RX and thus
      build the interrupt support for distinct TX & RX ISRs.
      
      Also, cleanup handling of UART_2..UART_4 to be similar to how
      UART_0/UART_1 code is using DT_INST_IRQN(x).
      
      Fixes #30770
      Fixes #25601
      Signed-off-by: default avatarKumar Gala <kumar.gala@linaro.org>
      ec0aa833
  11. 07 Apr, 2021 3 commits
    • Gustavo Romero's avatar
      tests: Add test to check uart_irq_is_pending · 92e00512
      Gustavo Romero authored
      
      Add test to check if uart_irq_is_pending() correctly returns 0 (meaning
      there are no more RX and TX pending interrupts) when all RX and TX data
      is processed.
      Signed-off-by: default avatarGustavo Romero <gustavo.romero@linaro.org>
      92e00512
    • Gustavo Romero's avatar
      drivers: uart: uart_cmsdk_apb: Fix uart_irq_is_pending · bd0fe17f
      Gustavo Romero authored
      Currently CMSDK uart_irq_is_pending does not use RX and TX interrupt
      bits found in INTSTATUS register to check for pending interrutps but
      rather it checks for pending interrupts indirectly by checking if RX and
      TX buffers are, respectively, full and empty, i.e. it checks bits 0 and
      1 in STATE register instead of bits meant for interrupt status found in
      INTSTATUS register.
      
      That is particularly problematic because although a RX interrupt implies
      a RX buffer full and a TX interrupt implies a TX buffer empty, the
      converse is not true. For instance, a TX buffer might be empty for all
      data was processed (sent to serial line) already and no further data was
      pushed into TX buffer so it remained empty, without generating any
      additional TX interrupt. In that case the current uart_irq_is_pending
      implementation reports that there are pending interrupts because of the
      following logic:
      
      /* Return true if rx buffer full or tx buffer empty */
      return (UART_STRUCT(dev)->state & (UART_RX_BF | UART_TX_BF))
                                      != UART_TX_BF;
      
      which will return 1 (true) if STATE[0] = 0 (TX buffer is empty), since
      UART_TX_BF = 1, so STATE[0] != UART_TX_BF, which is true (assuming here
      for the sake of simplicity that UART_RX_BF = 0, i.e. RX buffer is empty
      too).
      
      One of the common uses of uart_irq_is_pending is in ISR in contructs
      like the following:
      
      while (uart_irq_update(dev) && uart_irq_is_pending(dev)) {
        if (uart_irq_rx_ready(dev) == 0) { // RX buffer is empty
          continue;
        }
        // RX buffer is full, process RX data
      }
      
      So the ISR can be called due to a RX interrupt. Upon finishing
      processing the RX data uart_irq_is_pending is called to check for any
      pending IRQs and if it happens that TX buffer is empty (like in the case
      that TX interrupt is totally disabled) execution gets stuck in the while
      loop because TX buffer will never transition to full again, i.e. it will
      never have a chance to have STATE[0] = 1, so STATE[0] != UART_TX_BF is
      always true.
      
      This commit fixes that undesirable and problematic behavior by making
      uart_irq_is_pending use the proper bits in the interrupt status register
      (INTSTATUS) to determine if there is indeed any pending interrupts.
      
      That, on the other hand, requires that the pending interrupt flags are
      not clearly automatically when calling the ISR, otherwise
      uart_irq_is_pending() will return immediatly false on the first call
      without any data being really processed inside the ISR. Thus, because
      both RX and TX buffer (FIFO) are only 1 byte long, that commit clears
      the proper interrupts flags precisely when data is processed (fifo_read
      and fifo_fill) or when the interrupts are disabled (irq_rx_disable and
      irq_tx_disable).
      
      Finally, that commits also takes the chance to update some comments,
      specially regarding the need to "prime" when enabling the TX interrupts
      (in uart_cmsdk_apb_irq_tx_enable()). The need to "prime" can be verified
      in the CMSDK UART reference implementation in Verilog mentioned in the
      "Arm Cortex-M System Design Kit" [0], on p. 4-8, section 4.3,
      in cmsdk_apb_uart.v. In that implementation it's also possible to verify
      that the FIFO is only 1 byte long, justifying the semantics that if
      buffers are not full (STATE[0] or STATE[1] = 0) they are _completly_
      empty, holding no data at all.
      
      [0] https://documentation-service.arm.com/static/5e8f1c777100066a414f770b
      
      Signed-off-by: default avatarGustavo Romero <gustavo.romero@linaro.org>
      bd0fe17f
    • Gustavo Romero's avatar
      boards: arm: mps2-an521: Fix DT memory regions · fe3f71bd
      Gustavo Romero authored
      
      Currently RAM region specified in the DT for board mps2-an512 to store
      data (not to run code) is set to start at 0x3000_0000 and a 16M
      contiguous space is assumed. However, at that address there is no such
      contiguous space of 16M, rather only a 128K area is available. As a
      consequence large applications linked with Zephyr might end up using
      memory regions that are not valid, specially at runtime when the stack
      grows, causing a BusFault.
      
      Application Note 512 only specifies a 16M contiguous space available
      starting at 0x8000_0000 (please see 'Table 3-4: SSRAM2 and SSRAM3
      address mapping' and 'Table 3-6: External PSRAM mapping to Code Memory',
      on pages 3-7 and 3-8, respectively), which resides in the PSRAM
      (external RAM).
      
      The AN521 also specifies a 4M contiguous space available starting at
      0x3800_0000 which can be used as RAM for data storage and which is not
      currently described in the DT.
      
      The current DT also defines a 224M flash region (to run code) which
      doesn't effectively exist, because most of it is reserved (~148M).
      
      That commit fixes the incorrect definition of region 0x3000_0000 (16M)
      and hence defines a new region called 'sram2_3' that maps to region
      0x3800_0000 (4M) which is used as RAM to store data, and fixes the flash
      region defining a new region 'sram1' (4M) from where code is executed
      (starting at 0x1000_0000). The board has no real flash memory, rather an
      auxilary HW populates the appropriate memory regions from images found
      in a MicroSD card.
      
      That commit also defines the missing PSRAM (16M) region ('psram') which
      can be used by large programs as a general purpose RAM.
      
      Finally, it also fixes the DT for the non-secure memory regions to
      reflect the fixes described above for the secure memory regions.
      Signed-off-by: default avatarGustavo Romero <gustavo.romero@linaro.org>
      fe3f71bd
  12. 06 Apr, 2021 16 commits
  13. 26 Mar, 2021 1 commit
    • Eugeniy Paltsev's avatar
      linker-defs: Fix sorting order of objects by priority · 6c2ae13e
      Eugeniy Paltsev authored
      Commit 0a7b65ef
      
       tweaked the CREATE_OBJ_LEVEL macro in such a way
      that it would break the expected sorting order.
      
      For example if you had 2, 19, 20, 30 as the level, we'd end up sort
      these to be 19, 2, 20, 30.
      
      Fix this by adding aditional "_" symbol after the init level counter.
      That allows to keep correct sort order (for both GNU and MWDT
      toolchains) and distinguish init level counter from section suffix
      (for MWDT toolchain).
      
      Fixes zephyrproject-rtos#33464
      Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      6c2ae13e
  14. 22 Mar, 2021 2 commits
  15. 19 Mar, 2021 1 commit
    • Vinayak Kariappa Chettimada's avatar
      Bluetooth: controller: Fix regression in ctrl tx queue handling · 0249a626
      Vinayak Kariappa Chettimada authored
      Fix control Tx buffer leak into data Tx pool that happens
      after a cross-over control procedure response was paused due
      to currently active encryption setup procedure, and a new
      control Tx PDU in addition to the paused one is enqueued
      thereafter.
      
      When the control tx PDUs is resumed but not yet enqueued
      towards the radio, if there is a new control Tx PDU enqueued
      then the paused control Tx PDU is not set as the head of the
      control PDUs in the Tx queue. This caused the paused control
      Tx PDU to be associated with data Tx pool, hence causing the
      incorrect release into data Tx pool.
      
      Relates to the commit bff76b4c ("Bluetooth: controller:
      split: Fix control tx queue handling") and to the
      commit 6991d099
      
       ("Bluetooth: controller: Fix control tx
      queue handling").
      
      Fixes #32898.
      Signed-off-by: default avatarVinayak Kariappa Chettimada <vich@nordicsemi.no>
      0249a626
  16. 18 Mar, 2021 1 commit