1. 04 Jun, 2021 9 commits
    • Anas Nashif's avatar
      size_report: give root node a unique identifier · 39354d92
      Anas Nashif authored
      
      Call the root node 'root', otherwise we end up with two nodes with the
      same identifier ':'.
      Signed-off-by: default avatarAnas Nashif <anas.nashif@intel.com>
      39354d92
    • Andy Ross's avatar
      boards/x86/acrn: Use APIC_TSC_DEADLINE_TIMER · 45bd3dee
      Andy Ross authored
      
      This board got forgotten when we migrated the older APIC_TIMER users.
      Now the platform is SMP by default and the older driver refuses to
      build.
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      45bd3dee
    • Andy Ross's avatar
      boards/x86/acrn: Rework board documentation · 3da652f4
      Andy Ross authored
      
      ACRN build and configuration is non-trivially complicated, and so far
      integration documentation has been mostly missing, and users have had
      to get by via copying from existing integration efforts with minor
      changes, leading to repeated mistakes and persistent confusion.  This
      is an attempt to document the process from first principles, with an
      eye toward informing integrators (not me!) who might come by later to
      better automate things.  Some of the content is going to look remedial
      to someone already familiar with e.g. ACRN configuration or EFI boot.
      
      This simply replaces the pre-existing docs, which were for earlier
      versions of ACRN where Zephyr was launched from the service OS instead
      of the now-standard pre-launch VM mode.
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      3da652f4
    • Andy Ross's avatar
      boards/x86/acrn_ehl_crb: Enable SMP by default · c6f3887e
      Andy Ross authored
      
      SMP is working now, make a 2-cpu configuration default for this
      device.
      
      Note that this requires changes to the default ACRN build
      configuration!  In hybrid.xml, you need to specify multiple physical
      CPUs for the VM to uses, e.g.:
      
          <vm id="0">
              ...
              <cpu_affinity>
                  <pcpu_id>0</pcpu_id>
                  <pcpu_id>1</pcpu_id>
              </cpu_affinity>
          </vm>
      
      Failing to build with this change will result in the system hanging at
      boot trying to start up a CPU that won't run.
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      c6f3887e
    • Andy Ross's avatar
      boards/x86/acrn: Add APIC IDs · f479d5c7
      Andy Ross authored
      
      The ACRN hypervisor uses 0, 2, 4, 6 as its local APIC IDs for
      virtualized CPUs and not the 0, 1, 2, 3 defaults we have.
      
      (I hate this feature, having to manually (!) probe and code these
      things in C isn't scaling.  Zephyr needs to do the probing on its own
      somehow, even if it's an offline tool in Linux or something.)
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      f479d5c7
    • Andy Ross's avatar
      arch/x86_64: Use modern CR0 assembly · 9cb8dcbf
      Andy Ross authored
      
      The 16 bit bootstrap code for SMP CPUs was using the 286-era "lmsw"
      instruction (load machine status word) to set the protected bit in CR0
      (which is the modern evolution of the same register), presumably
      because this is 16 bit code and we can't move a dword into CR0.
      
      But that's wrong, because the full instruction set *is* available in
      real mode on a 386, you just have to use a operand size prefix to get
      to it, which the assembler emits for you automatically when you use
      the .code16 directive.
      
      Write this conventionally and use modern (e.g. 1986-era) instructions.
      It also has the advantage of not confusing much more modern
      hypervisors like ACRN by issuing instructions they (and I!) never knew
      existed.
      
      Fixes #35076
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      9cb8dcbf
    • Andy Ross's avatar
      arch/x86_64: Terrible, awful hackery to bootstrap entry · 5e9c583c
      Andy Ross authored
      
      Because of a historical misunderstanding, by default the ACRN
      hypervisor wants to load Zephyr at address 0x1000 and enter the binary
      at that same address.  This entry point corresponds to the __start
      symbol of the build they were given, which is a 1-cpu non-SMP
      configuration.  Unfortunately, when we build with
      CONFIG_MP_NUM_CPUS=1, the code in locore.S #if's out the 16 bit entry
      point for the auxiliary CPUs at the start of the section.  So in the
      build ACRN received, the start address happened to be 0x7000, the same
      address we need to launch the AP processors from.
      
      That's right: under ACRN, the SAME ADDRESS used to enter the OS in 32
      bit mode needs to be used later to boot CPUs running in 16 bit real
      mode!
      
      The solution, such as it is, is to put a 32 bit jump at the entry
      address which hops to the 32 bit OS entry code, and then scribble NOP
      instructions over that jump once we get there so that the next time we
      reach that address (in real mode) we fall through to the correct
      entry.
      
      This patch should be considered a temporary workaround.  While it
      works on all x86 hardware, it's not really needed.  A much better
      solution would be to eliminate the locore linker region entirely
      (which causes other headaches) and enter the Zephyr binary in a 32 bit
      address somewhere in the contiguous high memory area.  All that locore
      is needed for is the 16 bit bootstrap code for SMP processors, which
      is ~6 instructions and can be copied in from the kernel at runtime.
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      5e9c583c
    • Jennifer Williams's avatar
      logging: log_msg.c: fix coding guideline 15.7 missing comment · d6a3679c
      Jennifer Williams authored
      
      The final else {} in the if...else if is missing required
      comment (non-empty, ';' is not sufficient). This adds a comment
      to comply with CG 15.7.
      Signed-off-by: default avatarJennifer Williams <jennifer.m.williams@intel.com>
      d6a3679c
    • Jennifer Williams's avatar
      logging: log_core.c: fix coding guideline 15.7 missing comment · 09ee9d6e
      Jennifer Williams authored
      
      The final else {} in the if...else if is missing required
      comment (non-empty, ';' is not sufficient). This adds a comment
      to comply with CG 15.7.
      Signed-off-by: default avatarJennifer Williams <jennifer.m.williams@intel.com>
      09ee9d6e
  2. 03 Jun, 2021 17 commits
  3. 02 Jun, 2021 14 commits